Freescale Semiconductor /MKL24Z4 /UART0 /C5

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Interpret as C5

7 43 0 0 00 0 0 0 0 0 0 0 0 (0)RESYNCDIS 0 (0)BOTHEDGE 0 (0)RDMAE 0 (0)TDMAE

TDMAE=0, RESYNCDIS=0, RDMAE=0, BOTHEDGE=0

Description

UART Control Register 5

Fields

RESYNCDIS

Resynchronization Disable

0 (0): Resynchronization during received data word is supported

1 (1): Resynchronization during received data word is disabled

BOTHEDGE

Both Edge Sampling

0 (0): Receiver samples input data using the rising edge of the baud rate clock.

1 (1): Receiver samples input data using the rising and falling edge of the baud rate clock.

RDMAE

Receiver Full DMA Enable

0 (0): DMA request disabled.

1 (1): DMA request enabled.

TDMAE

Transmitter DMA Enable

0 (0): DMA request disabled.

1 (1): DMA request enabled.

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